| 摘要 |
PURPOSE:To deliver the output signals of plural process output devices to an object device in the same timing by delivering the data held by a memory means synchronously with a common clock signal. CONSTITUTION:A command signal sent from a CPU1 is supplied to a control circuit 302 of a process output device 21 via input/output bus line 101 and an input/output interface 301. Then the circuit 302 stores the prescribed data to buffer registers 3061-306n via a DMA bus line 102 in response to the address designation of the CPU1. Then the pulse of a common clock signal of cycle T is supplied to each control circuit 302 of each process output device, and therefore the data of registers 3061-306n are loaded collectively to output circuits 3071- 307n in the data loading timing. Then these output circuits deliver data to external devices.
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