| 摘要 |
PURPOSE:To obtain a monitor circuit for memory reading actin which applies an interruption to a CPU when no IC memory element is loaded by detecting and monitoring the floating state of a data bus during a cycle when the data is read out of the IC memory element by the CPU. CONSTITUTION:When an address is delivered from the CPU, an ROM address detecting part 9 detects whether or not the addresses of IC memory elements 10-17 are accessed for the upper position of the address. The output signal of the part 9 becomes active to enable a decoder 10. The decoder 10 decodes the middle position of the address and selects either one of elements 10-17. While a delay circuit 13 made active for the output after elapsing the maximum access time of the IC memory element when the memory read signal becomes active. Thus an AND circuit 14 is ANDed between the output of an AND circuit 8 and the output of the circuit 13. Then it is detected whether the outputs of the elements 10-17 are set under the floating states when the output of the circuit 13 becomes active. |
