| 摘要 |
PURPOSE:To perform A/D conversion at high speed without causing malfunction by increasing clock pulse frequency of a successive comparison type A/D converter continuously from high order side bit to low order side bit. CONSTITUTION:An analog signal from a terminal 7 is added with output from a DA converter 5 by an adder 1 and the result of addition is impressed to a comparator 2 that judges positive or negative of the polarity, and inputted to a successive comparison register 3 that set the content basing on the result of comparison. The DA converter 5 outputs binary weighted analog value to the adder 1 basing on digital output 4 of the register 3. Clock pulse CP from a clock oscillator 6 is processed by a controlling circuit 8, and frequency is changed to lower frequency for comparison of high order bit side and to higher frequency for comparison of low order bit side. The CP is impressed to the register 3 and comparison time is set longer in high order side bit. |
