| 摘要 |
For a binary segmented digital to analogue converter embodied in a monolithic semiconductor device, and with a fixed arrangement of sources 12, there being inevitably inaccuracies in the magnitudes of the source outputs, there is provided adjustable means, for example, a programmable read-only memory 30, having an appropriate, empirically derived setting, to determine the order positions of the sources in the sequence in which the sources, possibly additionally, are connected solely to the converter output, via a switching matrix 10, as the values represented by digital input signals to the converter increase from zero, whereby there is obtainable the maximum improvement in the accuracy of the converter in this respect, the consequentially determined increments in the overall stepped converter response, indicated (in Fig. 2, not shown) as A'', B' - - - - G'', H'', being closer to the increments of the ideal response, A, B - - - - G, H than the order positions of the sources in the sequence are arbitrary. <IMAGE> |
