发明名称 SEMICONDUCTOR LOGICAL CIRCUIT
摘要 PURPOSE:To attain high speed operation by connecting a drain of a P-channel MOS transistor (TR) for loading to an input terminal and also connecting the drain to a gate of an N-channel MOSTR for driving so as to provide a large current amplification factor to each MOS TR. CONSTITUTION:A P-channel TRM1 for loading is an enhancement type one and its threshold voltage VTH1 is selected to be sufficiently smaller than the built-in potential VFB1 of the P-N junction between the base and source. An N-channel TRM2 for drive is an enhancement type one and its threshold voltage VTH2 is selected to be sufficiently smaller than a built-in potential VBF2 of the P-N junction between the source and base. The current amplification factor beta1 of the MOSTRM1 is expressed as [beta1=betaM1+betaB1], where betaB1 is the current amplification factor of the MOSTRM1 as a bipolar TR. Similarly, as to the MOSTRM2, its current amplification factor beta2 is expressed as [beta2=betaM2+betaB2].
申请公布号 JPS607228(A) 申请公布日期 1985.01.16
申请号 JP19830114562 申请日期 1983.06.25
申请人 TOSHIBA KK 发明人 KOIKE HIDEJI
分类号 H03K19/094;H01L27/092;H03K19/0948;(IPC1-7):H03K19/094 主分类号 H03K19/094
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