发明名称 Method of Manufacturing a Semiconductor Device Having a Charge Compensation Region Underneath a Gate Trench
摘要 A method of forming a semiconductor device is provided. The device includes a semiconductor substrate having a main surface and a rear surface vertically spaced apart from the main surface, a first doped region, a second doped region and a third doped region. The third doped region is interposed between the first and second doped regions beneath the main surface. Field plate trenches having field plates vertically extend from the main surface to a bottom that is arranged in the first doped region. A gate trench having a gate electrode vertically extends from the main surface to the first doped region. A compensation zone vertically extends from the bottom of the gate trench deeper into the first doped region. The compensation zone is laterally aligned with the gate trench and is adjacent to the field plates along a cross-sectional plane of the device that is parallel to the main surface.
申请公布号 US2016372538(A1) 申请公布日期 2016.12.22
申请号 US201615251606 申请日期 2016.08.30
申请人 Infineon Technologies Austria AG 发明人 Jin Minghao;Yip Li Juin;Blank Oliver;Vielemeyer Martin;Hirler Franz
分类号 H01L29/06;H01L29/10;H01L29/78;H01L29/66;H01L29/40 主分类号 H01L29/06
代理机构 代理人
主权项 1. A method of forming a semiconductor device, the method comprising: forming a semiconductor substrate comprising a main surface and a rear surface vertically spaced apart from the main surface, a first doped region, a second doped region and a third doped region, the second and third doped regions being formed in the first doped region, the second doped region extending from the main surface into the substrate, the third doped region interposed between the first and second doped regions beneath the main surface; forming first and second field plate trenches vertically extending from the main surface to a bottom that is arranged in the first doped region; forming first and second field plates arranged in the first and second field plate trenches, respectively, and being dielectrically insulated from the substrate; forming a gate trench laterally arranged between the first and second field plate trenches and vertically extending from main surface through the second and third doped regions so that the gate trench has a bottom arranged in the first doped region; forming a gate electrode arranged in the gate trench and being dielectrically insulated from the substrate, the gate electrode being configured to control an electrically conductive channel in the third doped region; and forming a compensation zone vertically extending from the bottom of the gate trench deeper into the first doped region, wherein the compensation zone is laterally aligned with the gate trench from a plan view perspective of the main surface, wherein the compensation zone is adjacent to the field plates along a cross-sectional plane of the device that is parallel to the main surface, wherein the first and second doped regions have a first conductivity type, wherein the third doped region and the compensation zone have a second conductivity type.
地址 Villach AT