Microprocessor system for controlling or regulating at least partly safety-critical processes

摘要

A microprocessor system (50) for controlling or regulating at least partly safety-critical processes, comprising two central processing units (1, 2) integrated in a chip housing, a first and a second bus system, at least one full memory (7) on the first bus system, at least one test data store (51) on the second bus system, which has a reduced store coverage compared to the full memory on the first bus system and in which test data are stored which are connected to data of the memory (7) on the first bus system, and the bus systems comprise comparison and/or driver components which allow the data interchange and/or comparison of data between the two bus systems, and a hardware test data generator (4) is arranged at least on the second bus system, in which case at least part of the full memory on the first bus is additionally backed up using another test data store (5) and test data on the first bus. The invention further relates to the use of the above microprocessor system in motor vehicle controllers.

主权项

1. A microprocessor system for controlling at least partly safety-critical processes, comprising:
a first central processing unit and a second central processing unit integrated in a chip housing, the first and second central processing units being configured to operate in clock synchronism with each other; a first bus system associated with the first central processing unit and a second bus system associated with the second central processing unit; at least one full memory on the first bus system; a first test data store on the second bus system, the first test data store having a reduced storage compared to the full memory on the first bus system, the first test data store storing test data related to data in the memory on the first bus system; each of the first and second bus systems including components which allow data interchange and comparison of data between the two bus systems; a first hardware test data generator arranged on the first bus system, the first hardware test data generator being configured to check the data according to at least one test data generation method and further being configured to correct the data in response to at least one type of data error; a second hardware test data generator arranged on the second bus system, the second hardware test data generator being configured to check the data according to at least one test data generation method; and wherein at least part of the full memory on the first bus is additionally backed up by means of a second test data store on the first bus, the second test data store storing test data and being configured to check corrected data from the first hardware test data generator.