发明名称 FLIP FLOP CIRCUIT
摘要 PURPOSE:To constitute an FF circuit with a small number of elements by combining NOR circuits having plural outputs which consist of plural transistors whose bases receive the same potential supplied from plural parallel input TRs. CONSTITUTION:An input stage is constituted with input TRs Tr1-Tr3 whose collectors and emitters are connected one another and resistances R1 and R2 which are connected to an earth point VCC and a power source voltage VEE respectively, and an output stage is constituted with emitter follower circuits EF1 and EF2 consisting of TRs Tr4 and Tr5 whose bases receive the potential of a connection node (n) of the resistance R1 and TRs Tr1-Tr3, thus constituting a non-threshold logic NTL circuit, If one of input signals Vin1-Vin3 becomes high-level at least, TRs Tr4 and Tr5 are turned off, and outputs are in the low level together, and this circuit is operated as a NOR circuit having three inputs and two outputs. Data D, a clock CK, and a set signal S are supplied to NOR circuits G11-G13 of this constitution, and a reset signal R is supplied to a NOR circuit G21 of the next stage, thus constituting the FF circuit.
申请公布号 JPS6055719(A) 申请公布日期 1985.04.01
申请号 JP19830163149 申请日期 1983.09.07
申请人 HITACHI SEISAKUSHO KK;NIPPON DENSHIN DENWA KOSHA 发明人 ISHII SHIYUUICHI;USAMI MITSUO;HORIGUCHI KATSUJI;HIRATA MICHIHIRO
分类号 H03K3/037;(IPC1-7):H03K3/037 主分类号 H03K3/037
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