| 摘要 |
PURPOSE:To obtain a power CMOS IC having a much more enhanced withstand voltage by a method wherein the drain diffusion layer of a transistor to be formed in a well is made as a diffusion layer deeper than diffusion depth of the drain of a transistor to be formed in a substrate. CONSTITUTION:An N type well 2 is formed in a P type semiconductor substrate 1, an N-channel transistor 3 having a source 5, a drain 6 and a gate 7, and a P- channel transistor 4 having a source 9, a drain 13 and a gate 11 are formed, and diffusion depth of the drain diffusion layer 13 is decided properly from the necessitating withstand voltage as deeper than the diffusion layer 6. Accordingly, the withstand voltage of the transistor 4 is enhanced, and a power CMOS IC having an enhanced withstand voltage can be obtained even when concentration of the well, etc. are not thinned. |
