| 摘要 |
PURPOSE:To simulate the actually returning state of an error signal by returning a signal RDY as a signal ERR only when the counted value of a counter for counting the rising point of the signal RDY coincides with a set value. CONSTITUTION:When switches 3a, 3c are turned off and other switches are turned off as an example, logic ''1'' is obtained from terminals 0, 2 of a multiplexer 4 and logic ''0'' is obtained from other terminals. Therefore, a signal (e) of logic ''1'' is outputted from a terminal Y only at the phases of No.0 (A' B' C') and No.2 (A' B C') out of eight phases of No.0-No.7. A signal RDY is inverted by an inverter 6, the inverted signal is inputted to one input of a gate 9 and a signal passed through the gate 9 is inverted by an inverter 10, so that a signal (f) is obtained as a false error signal. |
