| 摘要 |
PURPOSE:To determine a test mode of a semiconductor integrated circuit without providing an exclusive test terminal by processing logically the outputs of shift registers of plural stages driven by a clock input and a reset input, and determining the test mode. CONSTITUTION:Clock and reset signals are supplied to data terminals D and clock terminal CLs of the first stages of shift registers 4 of plural stages, for instance, four stages, etc. through invertors 6, 7, respectively, from a clock input terminal 2 and a reset input terminal 3 of a semiconductor integrated circuit 1, and the register 4 is driven. Subsequently, the reset signal and the output of each stage of the register 4 are supplied to a logical processing circuit 5 formed by a NAND gate and the invertor, an output of the circuit 5 is determined clearly by a state of the register 4, and only when a code of the register 4 is 0110 and the reset signal is ''1'', etc., a test mode output of ''1'' is generated from the circuit 5. According to this constitution, the test mode of the semiconductor integrated circuit can be determined without providing an exclusive test terminal. |
