发明名称 MOS TYPE INSULATED GATE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To prevent the generation of a negative breakdown phenomenon occurring from formation of a short channel and a high electric field by a method wherein the ratio of the channel width and the channel length of an MOS type insulating gate field-effect transistor is constituted at 5 or below. CONSTITUTION:When the two MOS type FET Tr 1 and Tr 2 having a different gate length and a gate width are compared, their thermal current density and electric field located in the drain depletion layer are considered equal, and in spite of the fact that the electric charge 4, among the injection electric charge from a source, which is lost without reaching the end of the drain depletion layer, which is the region where impact ions are generated, of the Tr 1 and Tr 2 are same, it is clear that the total quantity of injection electric charge from a source junction is larger on the Tr 1, which has a wider gate width. To be more precise, the relative injection efficiency of the electric charge which contributes to the generation of negative breakdown on the drain depletion layer is enhanced as the gate width becomes wider. By having the ratio W/L of the gate width W and the gate length L at 5 or below, the negative breakdown generating voltage is boosted, thereby enabling finally to prevent the generation of negative breakdown.
申请公布号 JPS60214557(A) 申请公布日期 1985.10.26
申请号 JP19840071255 申请日期 1984.04.10
申请人 NIPPON DENKI KK 发明人 OOOKA HIDEYUKI
分类号 H01L21/8234;H01L27/088;H01L29/10;H01L29/78 主分类号 H01L21/8234
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