| 摘要 |
PURPOSE:To supervise simply the operation of a buffer circuit by counting number of 1s or 0s of an input digital signal subject to frame synchronization in the unit of N frames, applying time division multiplex to the result of count, inputting the result to a buffer circuit for processing. CONSTITUTION:Number of 1s or 0s in an input digital signal (a) synchronized with a frame synchronizing circuit 1 is counted by a counter circuit 2 at each N-frame, the result of count is inputted to a time division multiplex circuit 3, where the signal is subject to multiplex in the time slot of a frame synchronizing signal from the circuit 1. The multiplexed signal (d) is inputted to a delay circuit 4 being a buffer circuit, and a digital signal is obtained after being delayed in the unit of bits for a prescribed amount. The number of 1s or 0s of the signal (e) is counted by a counter circuit in the unit of N frame, an output (g) and the result of count of the circuit 2 subject to time division multiplex in the time slot of the signal (e) are compared by a comparator circuit 6 and the operation of the circuit 4 is supervised. When the dissidence is detected by the circuit 6, it is discriminated that an error takes place in the circuit 4. |
