INTEGRATION TESTING CIRCUIT

摘要

PURPOSE:To reduce the time for testing by decoding the signal from a bus line and generating an optional timing signal in the stage of testing an IC. CONSTITUTION:A data selector 15 which selects and outputs alternately the output from a counter 11 and the output of an address bus is provided in an LSI10 having a decoder 12 which decodes the count values of the counter and generates various timing signals and a control part 14 which processes the various signals obtd. from an input and output part 13 on the basis of the decoded outputs. The output of the address bus is then selected as the input to the decoder 12 and the same value as the count value of the counter 11 suitable for a test item is supplied from the outside in the test stage. The optimum timing meeting the object of the test is thus obtd. by controlling optionally the various timing signals outputted from the decoder 12 from the outside.