发明名称 METHOD OF MAKING INTEGRATED BIPOLAR TRANSISTORS OF VERY SMALL DIMENSIONS
摘要 A process is provided for manufacturing bi-polar transistors integrated on silicon. To form transistors of very small dimensions, a layer of polycrystalline silicon is deposited (after a localized oxidization step) which is etched and which is doped so as to serve as doping source for P+ extrinsic base regions of the transistor. After doping of the P intrinsic base, the oxide and/or nitride is then deposited at low pressure which is implanted with an impurity facilitating dissolution thereof. On the vertical walls of the polycrystalline silicon around the base, the nitride is not dissolved. Elsewhere it is easily dissolved. Advantage is taken of the oxide or nitride thickness which remains to form by diffusion of an N+ emitter region which will not extend laterally as far as the P+ type extrinsic base but which will allow to remain an intrinsic base of very small thickness. The emitter diffusion may take place through a second polycrystalline silicon layer.
申请公布号 DE3271346(D1) 申请公布日期 1986.07.03
申请号 DE19823271346 申请日期 1982.06.24
申请人 THOMSON-CSF 发明人 ROCHE, MARCEL
分类号 H01L21/033;H01L21/331;H01L29/41;(IPC1-7):H01L21/00;H01L21/285;H01L21/60 主分类号 H01L21/033
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