Parallel image processor.

摘要

An LSI parallel image processor in which line buffers (20-i) and data-flow switching circuits (70) each requiring a larger amount of hardware in the prior art are incorporated into an LSI circuit, the image data delayed by the line buffers (20-i) is output from an image data output port (55), shift registers (31-i) each having a variable number of steps for preserving local image regions are intermittently shifted-in in accordance with applied clocks, and the contents of the shift registers (31-i) are sequentially read out.