BASIC CELL FOR MASTER SLICE

摘要

PURPOSE:To improve the density of a main wiring at master slicing time by disposing local wirings for enabling connections between transistors on an insulating layer formed to include the gate electrodes of the transistors. CONSTITUTION:Local wirings 11 for enabling connections between transistors are disposed on an insulating layer 10 formed to include gate electrodes 1 of the transistors. Main wirings at master slicing time are formed on an insulating layer formed on the wirings 11. Accordingly, it is not disturbed by the wirings 11 to enable to dispose to cross the wirings 11.