Apparatus for reducing test data storage requirements for high speed VLSI circuit testing.
摘要
<p>Apparatus for applying for a plurality of test cycles data specifying a plurality of test conditions to a multiple pin electronic circuit. A random access memory includes at a plurality of higher order addresses a complete data field for a plurality of test cycles. Some of said data fields include an operational code indicating that a minority of data bits in a field are to change in a consecutive number of following test cycles. A hold register is connected to receive each addressed row of test data from the memory. The higher order addresses of a memory addressed to produce complete data fields in the hold register. An operational code will be decoded to indicate a number of subsequent consecutive test cycles where a minority of data in the hold register are to be changed. The lower order addresses of the memory are subsequently addressed for a number of consecutive test cycles indicated by the operational code. The data contained in the lower order memory addresses is inserted in the hold register without changing the contents of a majority of hold register data bits.</p>
申请公布号
EP0204130(A2)
申请公布日期
1986.12.10
申请号
EP19860105724
申请日期
1986.04.25
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人
MILLHAM, ERNEST H.;MOSER, JOHN J.;SHUSHEREBA, JOHN J.;VISCO, GARY P.