发明名称 SYNCHRONIZING CLOCK REPRODUCING DEVICE
摘要 PURPOSE:To adjust always optimumly and automatically the identifying level of an input signal and to obtain a satisfactory synchronizing clock signal by integrating a identifying level correcting signal fed from the code deciding device and providing an accumulating part to adjust the identifying level. CONSTITUTION:At a conventional synchronizing clock reproducing device, a code deciding device 11 and an accumulating part 15 are provided. In the deciding device 11, it is decided whether the zero cross point of the input signal is generated by the rise or by the fall, then, the phase error signal code is decided and the identifying level correcting signal is outputted. The correcting signal, in the accumulating part 14, is accumulated, attenuated and made into the identifying off-set signal, the signal is changed, and the identifying level is always optimumly kept. For such a reason, the satisfactory synchronizing clock signal can be obtained.
申请公布号 JPS61283077(A) 申请公布日期 1986.12.13
申请号 JP19850124114 申请日期 1985.06.10
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SHIMADA TOSHIYUKI
分类号 G11B20/14;H03K5/00;H03L7/06 主分类号 G11B20/14
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