| 摘要 |
PURPOSE:To attain stable operation of a semiconductor memory device by compensating the decrease of a voltage level on a bit line at rewriting without increasing the capacity on the bit line. CONSTITUTION:A clock signal P1 is fed respectively to a coupling capacity CC through transistors (TRs) T5, T6 whose conducting state is controlled by using a clock signal P2. TRs are n-channel MOS TRs. When the clock signal P1 reaches a high level, TRs T5, T6 are nonconductive and the level amplitude VC of nodes N1, N2 is decreased by the value. That is, in bringing the low level potential of the clock signal P1 to a common potential, the level amplitude of the nodes N1, N2 is obtained by selecting V20>VT and the reduction of the VC is compensated by increasing the coupling capacitance CC.
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