发明名称
摘要 PURPOSE:To prepare an address alteration table automatically by omitting data writing in an address alteration table at the stage of the initial production of a memory device using memory elements in which defective places exist at random and testing the table just before the use of it. CONSTITUTION:A data read out from a normal memory element MEM-N accessed by a normal address scanner ADS-N is stored in a register RDR-N and checked by a circuit CHK. When there is no error, valid indication is written in an address alteration table ATT by using a write data register WDR-T. A scanner ADS-N advances the address by 1 step and, if the address is the maximum address of the element MEM-N, the preparation of the table ATT is ended. When an error is detected, and circuit CHK inputs an alteration address A-A from an alteration address scanner ADS-A to an alteration memory element MEM-A and an address alteration table data register WDR-T. Then the alteration address is checked in the circuit CHK and, if there is no error, it is written in the table ATT.
申请公布号 JPS6235707(B2) 申请公布日期 1987.08.03
申请号 JP19810045930 申请日期 1981.03.29
申请人 FUJITSU LTD 发明人 TAKAMURA MORYUKI
分类号 G06F12/16;G06F11/20;G11C29/08 主分类号 G06F12/16
代理机构 代理人
主权项
地址