| 摘要 |
<p>PURPOSE:To output a clock whose level is not overlapped by forming a clock driver circuit by 2-stage of output stage driveres and an inverter group causing a signal delay to drive p-channel and n-channel MOS elements at the output stage. CONSTITUTION:Q1, Q3 are p-channel MOS elements and Q2, Q4 are n-channel MOS elements, and when an input 1 rises, a signal 3 turns on the element Q2 and an output 7 goes down to a low level. Then the element Q3 is turned on by an output 6 delayed by 3-stages of inverters from the signal 3 and an output 8 goes to high level. That is, the output 8 is obtained after the output 7 goes to a low level at the point of time then no high level is overlapped. When the input 1 changes from a high level to a low level, the output 2 turns on the element Q4, the output 8 goes to a low level, the output 5 turns on the element Q1, the output 7 goes to a high level and no high level is overlapped between the outputs 7, 8.</p> |
