发明名称 SEMICONDUCTOR MEMORY CIRCUIT
摘要 PURPOSE:To attain a high speed operation and to improve the holding characteristic of memory information by preventing the node potential of a memory cell during a reading from being changed by having the prescribed relation of a word line potential and a data line potential. CONSTITUTION:At the time of reading the memory cell 101 of cross connections FET102, 103 or the like, the word line 112 is raised from a low power source potential to a potential VW=0V. This potential is smaller than the sum of the potential VD of the data lines 151, 152 and the threshold voltage VTH of data transmitting FETs 108, 109, and only the FET 108 or 109 of the low potential nodes 106, 107 side is turned on. Accordingly, the substantial potential of the nodes 106, 107 is not changed but the large potential difference which is not changed before the reading is supplied to the base of the FETs 153, 154 of a differential amplifier 160 through the jitter lines 151, 152. At the time of writing, VW>VD+VTH and the potential difference of the nodes 108, 109 of the cell 101 is enlarged. Thereby, the memory cell is operated at high speed, the holding characteristic of the memory information is improved and the information rupture strength due to alpha-ray irradiation is enhanced.
申请公布号 JPS62245592(A) 申请公布日期 1987.10.26
申请号 JP19860089012 申请日期 1986.04.17
申请人 HITACHI LTD 发明人 HIGUCHI HISAYUKI;SUZUKI MAKOTO;HONMA NORIYUKI;ITO KIYOO
分类号 G11C11/41;G11C11/416;G11C11/418;G11C11/419 主分类号 G11C11/41
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