| 摘要 |
PURPOSE:To reduce the burden of a main processor and attain a small scale hardware constitution by switching two DMA (direct memory access) control circuits alternately for each frame to transfer continuously sent reception data. CONSTITUTION:After assembling reception data to character units, a high level data link (HDLC) receiving circuit 1 sends a DMA transfer request signal s1 and reception data D to a reception waiting circuit, for example, a control circuit 5 out of DMA control circuits 5 and 6 through a switching circuit 3. Data D is transferred to a memory 8 through the control circuit 5. When a detecting circuit 2 detects an end flag pattern in reception data to output a signal s2 or a signal s3 indicating the completion of data transfer of transfer bytes whose number is set to the control circuit 5 is outputted, a switching control circuit 4 sends a switching signal s6 to the switching circuit 3 to send the signal s1 and data D to the control circuit 6 and switches operation states of control circuits 5 and 6. While the switched control circuit 6 per forms the transfer operation, a main processor 7 sets trans fer instruction information of the transfer address and the number of transfer bytes of following reception data to the control circuit 5.
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