| 摘要 |
PURPOSE:To shorten a conversion time by varying a clock frequency when the output of an up/down counter converges to a value to be found. CONSTITUTION:When an analog input signal to a comparator 24 is greater than an analog value outputted from a D/A converter 23, the output of the comparator 24 advances together with a clock input from a clock controller 21 by placing an up/down counter 22 in up mode, and the output of the D/A converter 23 is increased. When the output of the D/A converter 23 exceeds the analog input, the counter 22 is set to a down side to decrease the output together with the clock input, and the output of the D/A converter 23 converges by alternating a value a little bit greater than the analog input value with a value a little bit less. In the fromer half period T1 of the convergence, a clock controller 21 supplies a clock with a frequency 2fc, and in the latter half period, it supplies a clock with a frequency fc. |
