发明名称 A method and a system for processing logic programs.
摘要 <p>In a method for processing logic programs - especially in Prolog-like languages - using at least one processor, which allows parallelism - also retroactively - by an existing process, called "father", creating at optional OR-parallel nodes at least one process, called "son", standing in an OR-parallel relationship to the father, a deep-binding list, called "hash-window" is created only for the newly created son in which - while processing the split-off OR-parallel branch - it performs bindings to variables commonly accessible to it and its father, called"commonly accessible variables."</p>
申请公布号 EP0252176(A1) 申请公布日期 1988.01.13
申请号 EP19860109342 申请日期 1986.07.08
申请人 EUROPEAN COMPUTER-INDUSTRY RESEARCH CENTRE GMBH 发明人 SYRE, J. C.;WESTPHAL, H.;HAILPERIN, M.
分类号 G06F9/44;G06F17/30;(IPC1-7):G06F9/44 主分类号 G06F9/44
代理机构 代理人
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