发明名称 |
Process for producing memory cell having stacked capacitor |
摘要 |
A process for producing a memory cell having a stacked capacitor. As the reduction in device size of memory cells progresses, it becomes difficult to obtain a satisfactorily large capacitance even with a stacked capacitor structure. To enable a larger capacitance to be obtained for the same occupied area, projections and recesses are provided on the surface of a capacitor electrode. It is possible, according to the process, to readily produce projections and recesses for increasing the storage capacitance.
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申请公布号 |
US4742018(A) |
申请公布日期 |
1988.05.03 |
申请号 |
US19860936602 |
申请日期 |
1986.12.01 |
申请人 |
HITACHI, LTD. |
发明人 |
KIMURA, SHINICHIRO;SUNAMI, HIDEO |
分类号 |
H01L27/04;H01L21/02;H01L21/822;H01L21/8242;H01L27/10;H01L27/108;(IPC1-7):H01L21/70;H01L27/00 |
主分类号 |
H01L27/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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