TWO-WIRE BUS-SYSTEM COMPRISING A CLOCK WIRE AND DATA WIRE FOR INTER CONNECTING NUMBER OF STATION

摘要

The system includes a number of stations which are interconnected by a clock bus wire and a data bus wire and a data bus wire both of which are provided with elements for forming a wired logic function of the signals generated on the wire by the stations. The stations include master and slave stations, each master station generating a clock pulse on the clock wire per bit cell. At least one transmitting station presents a data bit on the data wire per bit cell for a time period which covers the duration of the associated clock pulse.