| 摘要 |
Positive and negative time pulses are transmitted on a two-wire line (pulse line) for clock control. The pulse amplifier exhibits an input circuit (ES1, ES2, ES3) which can be matched to the pulse line (IL) and which is in each case followed by a DC-isolation stage for the positive and negative time pulses (ZIp, ZIn), which isolating stage is formed by optocouplers (OK1, OK3; OK2, OK4). The optocouplers (OK1-OK4) are followed by a pulse amplifier stage (VER) having in each case one input for the positive and negative time pulses. The pulse amplifier stage exhibits simple power MOS transistors which are driven by the optocouplers (OK1-OK4), the power transistors being formed by FET transistors (LT1-LT4) arranged in a bridge circuit. The power transistors (LT1-LT4) are operated independently of the operating voltage (UB), which can exhibit a value of 12-60 V, an auxiliary voltage (gate-source modulation voltage), which is approximately 10 V, being applied to the power transistors (LT1-LT4). Furthermore, a quick-response overload protection circuit (ÜSS) is allocated to the power transistors (LT1-LT4). <IMAGE>
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