EEPROM memory cell with two levels of polysilicon and a tunnel oxide zone.

摘要

The cell comprises a selection transistor (51), a pickup transistor (52), a thin oxide zone (56), a floating gate (58) superimposed on said thin oxide zone (56) and made with a first layer of polysilicon (57) in a single piece with a first gate (59) of the pickup transistor (52), and a control gate (61) superimposed on said first gate (59) of the pickup transistor (52) and made with a second polysilicon layer (61). The latter also forms the selection transistor gate (51) in a single piece.