| 摘要 |
<p>The bus mediation system has a number of modules (10,20,30), each of which has a CPU (11,21,31) and a bus control circuit (12,22,32). Each module shares a bus mediation circuit (1), a bus (2), a request signal line (3), a use-of-bus permission line (4) and a bus-is-busy signal line (5). The bus mediation circuit gives use-of-bus permission (BG) if the bus is not in use when a request signal is issued by one of the bus control circuits. Depending on its task level, each module decides whether it issues a request signal in the presence of request signals from other modules, and whether it keeps or abandons the acquired permit after finishing the process. This is made possible by providing each bus control circuits with hard wired logic circuit comprising AND, NAND, OR, NOR gates and flip-flops.</p> |
