发明名称 COMPUTER SYSTEM FOR VIRTUAL MEMORY CONTROL SYSTEM
摘要 PURPOSE:To effectively use an address exchange buffer TLB by adding together the contents of at least two prescribed fields among plural fields of a virtual address and using the result of said addition as an address or a part of this address for access of the TLB. CONSTITUTION:The contents (m bits) of the fields 33 and 34 of (a virtual address of) a virtual address register 32 are led to an adder 36. The result of addition (m bits) is loaded into a high order m-bit field of a TLB register 37. At the same time, the contents (n bits) of a field 35 of the register 32 are loaded into other n-bit fields of the register 37. The contents (m+n bits) of the register 37 are led to a TLB31 for reference to an entry designated by the TLB address within the TLB31. In such a way, a TLB can be effectively used.
申请公布号 JPS63159953(A) 申请公布日期 1988.07.02
申请号 JP19860306316 申请日期 1986.12.24
申请人 TOSHIBA CORP 发明人 UCHIBORI IKUO
分类号 G06F12/08;G06F12/10 主分类号 G06F12/08
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