| 摘要 |
PURPOSE:To obtain a dRAM with a large sense margin and to extend its refresh cycle by arranging dummy cells along dummy bit lines parallel to bit lines and selecting one dummy cell with one word line. CONSTITUTION:The dynamic type dRAM is provided with one dummy cell for each word line WL and also provided with a couple of dummy bit lines DBL for transferring information charges to and from those dummy cells DC; when a memory cell MC selected with some word line WL is connected to one bit line of a bit line couple PL, one dummy cell DC driven with this word line WL is connected to the other bit line BL from a dummy bit line DBL through a switch circuit. Only one dummy cell is therefore selected with one word line, so a reference potential written therein is left as it is for nearly the same time with the information potential of memory cells. Consequently, the potential of the dummy cell is fixed and the high sense margin is held for a long time.
|
