| 摘要 |
A data processing system has a host processor (100) and an interface processor (160) both accessing a RAM (136) via respective RAM address generators (128, 132). RAM control logic (122) coupled to the data bus (124) and associated with the interface processor (160) provides pre-decoding of op codes on the data bus and generates control signals. The control signals are used to speed up memory access by the interface processor, to provide memory address generation for the interface processor, or to control memory access by the interface processor.
|
