| 摘要 |
<p>A master slice type integrated circuit in which various circuits may be formed by varying the routing of interconnections, comprising a plurality of input/output cells (23) being arranged in a peripheral region on a semiconductor chip (20), a plurality of basic cell columns (22) each comprising a plurality of basic cells (21) arranged in a predetermined direction (A), each basic cell (21) constituting transistors, and an interconnection region (25) formed on the chip (20), for accommodating a data bus (55). The master slice type integrated circuit further comprises a plurality of latch cells (26) arranged in the basic cell columns (22), for keeping a potential of a data bus (55) laid on the interconnection region to prevent the data bus (55) from being changed into a floating state. Each latch cell (26) comprises transistors, each of which has a driving capability smaller than that of each transistor of the basic cell (21).</p> |
