| 摘要 |
<p>At each node of a ring there are receive (RX) and transmit (TX) shift registers in series with the ring for the transfer from and to the ring of packets of a common length, a receive clock data-locked to the received data for clocking the receive register (RX), and an independant transmit clock for clocking the transmit register (TX). The transmit clock is triggered on at the instant that a synchronisation bit in the packet is received in the receive register (RX), i.e. after a predetermined proportion of an input packet has been received.</p> |
