发明名称 MEMORY CIRCUIT WITH NOISE PREVENTING MEANS FOR WORD LINES
摘要 A memory circuit provided with improved noise preventing circuits allowing a high-density arrangement of memory cells is disclosed. The memory circuit comprises a cross-coupled circuit provided for adjacent two word lines. The cross-coupled circuit suppress the potential of one of the adjacent two word lines to a reference level when the other of the adjacent two word lines takes a selection level or a level near the selection level.
申请公布号 DE3379812(D1) 申请公布日期 1989.06.08
申请号 DE19833379812 申请日期 1983.09.12
申请人 NEC CORPORATION 发明人 WATANABE, HIROSHI
分类号 G11C11/413;G11C8/08;G11C11/408;(IPC1-7):G11C8/00 主分类号 G11C11/413
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