Watchdog timer.

摘要

In a watchdog timer, the selected codes identifying the format of a watchdog timer algorithm, such as the intervals within which a watchdog timer status must be issued by the host processor, are supplied as hardwired preset codes in programmable fuse or read only memory cells that are adapted to be programmed, but are immune from ESD, power glitches and errant software. A programmable code indicating a programmable time interval is also stored in a register protected from errant software when the watchdog timer is enabled. A selector receives the preset code and the programmable code and selects an output code indicating the time interval within which the watchdog timer must be reset by a processor status signal. The selector can be programmed to select only the preset code by supplying a selector control signal through an element that is immune from electrostatic discharge, power glitches and errant software. Also, a code fixing the watchdog timer in an on state can be supplied with ESD-immune cells. The watchdog timer employs a keyed sequence for the watchdog timer status signal.