| 摘要 |
<p>The logical address of the memory (12) is translated into a physical address on a series of successive levels and in branched form. The apparatus comprises a root table (27) which is addressed by a series of machine condition signals to provide a corresponding descriptor of the segment to be addressed. That descriptor, in combination with a part of the logical address, is used to address a table of segments (31), which in response can provide a descriptor of the page of memory to be addressed. The last-mentioned descriptor, in combination with another part of the logical address, is used to address a table of pages (32), which in response provides at least a part of the physical address. The apparatus comprises a cache memory (30) for storing a series of translation operations which have been effected. This memory is explored before the translation cycle which is initiated only if the logical address being sought is not among those stored thereby.</p> |
