发明名称 |
A HOLD VIOLATION FREE SCAN CHAIN AND SCANNING MECHANISM FOR TESTING OF SYNCHRONOUS DIGITAL VLSI CIRCUITS |
摘要 |
A sequential state element (SSE) is disclosed. In one embodiment, an SSE includes a differential sense flip flop (DSFF) and a completion detection circuit (CDC) operably associated with the DSFF. The DSFF is configured to generate a differential logical output. During a normal operational mode, the DSFF is synchronized by a clock signal to provide a differential logical output in a differential output state in accordance with a data input or in a precharge state based on the clock signal. The differential logical output is provided in a differential output state in accordance with a test input during a scan mode. The CDC is configured to generate a test enable input during the scan mode that indicates the scan mode once the differential logical output is in the differential output state. Accordingly, another SSE can be asynchronously triggered to operate in the scan mode without a separate scan clock. |
申请公布号 |
WO2016191383(A1) |
申请公布日期 |
2016.12.01 |
申请号 |
WO2016US33807 |
申请日期 |
2016.05.23 |
申请人 |
ARIZONA BOARD OF REGENTS, a Body Corporate of The State of Arizona, Acting for and on Behalf of ARIZONA STATE UNIVERSITY |
发明人 |
VRUDHULA, Sarma;KULKARNI, Niranjan |
分类号 |
H03K3/0233;H03K3/037 |
主分类号 |
H03K3/0233 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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