| 摘要 |
This invention relates to an interruption control method in a multi-processor system. A timer (11) generates periodically an interruption signal so that each interruption signal reaches each slave processor (31, 41, 51) at a time interval during which each slave processor (31, 41, 51) monopolizes a system bus (13) due to the delay action of each delay circuit (32, 42, 52). The time during which each slave processor (31, 41, 51) monopolizes the system bus (13) is predetermined to some extents. Therefore, each processor (31, 41, 51) can equally acquire the bus use right by determining in advance this time and letting an interruption signal reach each slave processor at this time interval. |
