Shared intelligent memory for the interconnection of distributed micro processors.

摘要

In a shared memory system, wherein several memory users MU(11) accede to a plurality of memory banks (17), a set of high level commands (CREATE, PUT, GET, RELEASE, ENQUEUE, DEQUEUE) is provided, to transfer data between a given memory user and the memory banks or another memory user. The high level commands sent by the memory users are built up by memory interfaces MI(13) connected to said memory users, and transmitted through an interconnection network (15) to Packet Memory Command Executors PMCE(12) integrated into each memory bank (17). The high level commands work with data records identified by Logical Record Addresses (LRA) known by the memory users. During execution of the high level commands by the PMCE (12), said LRA are translated into physical addresses corresponding to physical address space in the memory banks. Said physical address space dynamically is created and released upon need, through the Create or Release Commands. A given memory user is not involved at all by management of physical address space, and works only with the LRA of a record.