| 摘要 |
PURPOSE:To generate a middle-order group data signal without developing a high order group data signal to a low-order group data signal by inputting a high-order group frame, detecting each pattern from a signal of byte unit, and controlling the output phase of a developing circuit. CONSTITUTION:The high-order group data signal 101 and a high-order group clock signal 311 are inputted to the developing circuit 102, and the signal 101 is developed to a four system serial signal in byte unit. A separation circuit 109 takes out the signal of byte unit from developed four systems at every four bytes, and a parallel signal of eight bits and a clock signal from a four- frequency division circuit 306 are outputted. A low-order group frame appears in the parallel signal of eight bits from the circuit 109, and is branched to nine, and eight frames of frame synchronization circuits 103-1 to 103-8 and another one frame are supplied to a synchronization control circuit 110. And each synchronous circuit performs the detection of a specific pattern obtained by performing the patrol shift of prescribed frame pattern inserted to the low- order group frame at every bit, and a bit delay quantity is specified, and the output phase of the circuit 102 is controlled. |
