Receiver circuit and signal receiving method thereof

摘要

Provided is a receiver circuit which receives an input signal. A first restriction circuit provides a first reference voltage or an input signal higher than the first reference voltage to a first node. A second restriction circuit provides a second reference voltage or the input signal lower than the second reference voltage to a second node. A first PMOS transistor pulls up an output node based on a voltage of the first node, and a first NMOS transistor pulls down the output node based on a voltage of the second node. A second PMOS transistor is connected between the output node and the first PMOS transistor, and a second NMOS transistor is connected between the output node and the first NMOS transistor. At least one compensation resistor is connected between a power supply voltage and the first PMOS transistor or between the first NMOS transistor and a ground.

主权项

1. A receiver circuit which receives an input signal through a pad, the receiver circuit comprising:
a first restriction circuit configured to provide a first reference voltage or an input signal to a first node, the input signal having a voltage higher than the first reference voltage; a second restriction circuit configured to provide a second reference voltage or the input signal to a second node, the input signal having a voltage lower than the second reference voltage; a first PMOS transistor configured to pull up an output node based on a voltage of the first node; a first NMOS transistor configured to pull down the output node based on a voltage of the second node; a second PMOS transistor connected between the output node and the first PMOS transistor; a second NMOS transistor connected between the output node and the first NMOS transistor; and at least one compensation resistor connected between a power supply voltage and one end of the first PMOS transistor or between one end of the first NMOS transistor and a ground, wherein the first restriction circuit comprises a third PMOS transistor configured to provide the first reference voltage to the first node in response to the input signal.