发明名称 Apparatus and method for nullifying delayed slot instructions in a pipelined computer system
摘要 In a computing system which has memory and an instruction pipeline, a method and apparatus allows for nullification of a second instruction responsive to the state of a nullification field in a first instruction executed prior to the second instruction. After the first instruction is fetched, the operation specified by the first instruction is performed and the results of the operation are stored, including the state of the nullification field. The second instruction is fetched and the operation specified by the second operation is performed. However, conditional upon the state of the nullification field of the first instruction, results, errors, traps and interrupts of the second instruction are not stored in the computer system.
申请公布号 US5051896(A) 申请公布日期 1991.09.24
申请号 US19880170520 申请日期 1988.03.21
申请人 HEWLETT-PACKARD COMPANY 发明人 LEE, RUBY B.;BAUM, ALLEN J.
分类号 G06F9/32;G06F9/38 主分类号 G06F9/32
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