TERNARY ARITHMETIC AND LOGIC UNIT (ALU) AND TERNARY LOGIC CIRCUITS

摘要

A novel Ternary Arithmetic and logic Unit (TALU) comprising various logic circuit blocks, being an essential building block of central processing unit (CPU) of computing machines means digital computers, microprocessors, microcontrollers or similar machines, is proposed in the present invention, and for the execution of the said TALU, TRIT (ternary operator) having three discreet logic levels, means 0, 1, &2 (TRIT level) levels are implemented to realize logic unit (TALU) operation. The said implementation is achieved by the said gates using novel and dedicated combination of transmission gates (TG), whereas the said TG comprises enhancement mode CMOS transistors namely n-EMOS and p-EMOS having low output impedance, high input impedance and the combination of such TG is arranged in such a way that resistance, capacitor elements are dispensed with and the topology minimizes interconnections, reduces power consumption, decreases chip area, increases processing speed, increases circuit ability to work at low operating voltage, reducing output impedance, reduce noise. Following invention is described in detail with the help of Figure-1 of sheet 1 showing Plurality of 2 TRIT input TALU having n blocks in parallel.