发明名称 |
Reconfigurable semiconductor integrated circuit and electronic device |
摘要 |
According to an embodiment, a reconfigurable semiconductor integrated circuit includes memories connected in parallel, a logic circuit whose logic is defined according to data output of one of the memories, a signal output unit, and a switching unit. The signal output unit includes output terminals corresponding to the respective memories. Each terminal outputs a selection signal for enabling the data output or a non-selection signal for disabling the data output to the logic circuit. The signal output unit is configured to output the selection signal in a cyclic manner over the terminals so that one terminal outputs the selection signal and the others output the non-selection signal. The switching unit is configured to set a route between a first output terminal and a second output terminal of the terminals to an open state or a closed state. The route bypasses at least a single output terminal. |
申请公布号 |
US9525422(B2) |
申请公布日期 |
2016.12.20 |
申请号 |
US201615072890 |
申请日期 |
2016.03.17 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Oda Masato |
分类号 |
H03K19/003;H03K19/177;H03K19/173;G11C13/00;G11C11/41;G11C29/50;G11C17/18 |
主分类号 |
H03K19/003 |
代理机构 |
Finnegan, Henderson, Farabrow, Garrett & Dunner LLP |
代理人 |
Finnegan, Henderson, Farabrow, Garrett & Dunner LLP |
主权项 |
1. A reconfigurable semiconductor integrated circuit comprising:
a plurality of memories connected in parallel; a logic circuit whose logic is defined according to data output of one of the memories; a signal output unit including a plurality of output terminals corresponding to the respective memories, each output terminal outputting either a selection signal for enabling the data output or a non-selection signal for disabling the data output to the logic circuit, the signal output unit being configured to output the selection signal in a cyclic manner over the output terminals so that one of the output terminals outputs the selection signal and the others output the non-selection signal; and a switching unit configured to set a route between a first output terminal of the output terminals and a second output terminal of the output terminals either to an open state or a closed state, the route bypassing at least a single output terminal. |
地址 |
Tokyo JP |