Array substrate and method of manufacturing the same, and liquid crystal display screen

摘要

Embodiments of the present invention disclose an array substrate and a method of manufacturing the same, and a liquid crystal display screen. The array substrate comprises gate lines, data lines arranged to intersect the gate lines, common electrode signal lines, and a plurality of pixels defined by the gate lines and the data lines, wherein each pixel comprises a drive transistor, a pixel electrode connected with one of a source electrode and a drain electrode of the drive transistor while the other one of the source electrode and the drain electrode of the drive transistor is connected with the respective data line, and a common electrode electrically connected with the respective common electrode signal line, and, the common electrode signal lines and the gate lines are formed in the same layer and extend in the same direction as the gate lines, wherein each pixel further comprises a common electrode connection line formed in the same layer as the respective common electrode signal line and extending in a direction of the respective data line, and the common electrode connection line is electrically connected with the respective common electrode signal line and the respective common electrode. Embodiments of the present invention is made so that the pixel resistance value is reduced, reducing the phenomenon of partial green picture in the liquid crystal display screen as a whole.

主权项

1. An array substrate, comprising:
gate lines, data lines arranged to intersect the gate lines, common electrode signal lines, and a plurality of pixels units defined by the gate lines and the data lines, wherein each pixel unit comprises a drive transistor, a pixel electrode connected with one of a source electrode and a drain electrode of the drive transistor while the other one of the source electrode and the drain electrode of the drive transistor is connected with a respective data line, and a common electrode electrically connected with a respective common electrode signal line, the common electrode signal lines and the gate lines being formed in the same layer and the common electrode signal lines extending in the same direction as the gate lines, wherein each pixel unit further comprises a common electrode connection line formed in the same layer as the respective common electrode signal line and extending in a direction of the respective data line, and the common electrode connection line is electrically connected with the respective common electrode signal line and the respective common electrode which are located within the same pixel unit as the common electrode connection line.