Terminal architecture and control circuit.

摘要

Terminal architecture comprising a microprocessor (81) linked by a databus (8549), an address bus (8558) to a management circuit (85) for the video display and the accesses to a video memory VRAM (83) constituting the system memory and the display memory, the said management circuit (85) also being linked by an address bus (8528) and a databus (8529) to a character generator random-access memory (82) and by 5 output lines to the video monitor (8530, HRTL, VRT). <IMAGE>