Adaptive on-chip termination circuitry

摘要

An integrated circuit with on-chip termination (OCT) circuitry is provided. In particular, the integrated circuit may include an input-output (IO) buffer, an OCT circuit coupled between the IO buffer and a physical IO interface, and adaptive external OCT calibration circuitry for impedance matching the IO buffer to a transmission line that is coupled to the IO buffer. The adaptive external OCT calibration circuitry may include a waveform measurement circuit for selectively sampling a waveform at the IO interface, and a waveform analyzer and control circuit for analyzing the sampled waveform and adjusting the OCT circuit until the impedance provided by the OCT circuit matches with the external impedance of the transmission line. A switch that is interposed between the OCT circuit and the measurement module may be enabled during calibration and disabled during normal device operation.

主权项

1. An integrated circuit, comprising:
an external interface buffer; an on-chip termination (OCT) circuit that is coupled to the external interface buffer and that provides a termination impedance; a measurement circuit that monitors the termination impedance of the on-chip termination circuit; control circuitry that dynamically adjusts the termination impedance of the on-chip termination circuit based on the monitored result at the measurement circuit; and a switch that is coupled in series between the on-chip termination circuit and the measurement circuit, wherein the measurement circuit is prevented from monitoring the termination impedance of the on-chip termination circuit when the switch is open.